1. Field of the Invention
The present invention relates generally to a linearity improvement for a Field Effect Transistor (FET) amplifier and more specifically to two stage FET amplifiers using a feedback network in a second stage active bias circuit to achieve improved linearity at radio frequencies.
2. Description of the Prior Art
Many FET amplifier topologies have inherent nonlinearity which must be corrected in order to achieve optimal performance. Improved linearization allows an amplifier to operate at comparable output power with reduced intermodulation and reduced DC power consumption. FET gate biasing techniques to improve linearity are well known in the art but generally are very sensitive to small bias variations, yield only a modest improvement at radio frequencies, or increase the circuit's noise factor.
U.S. Pat. No. 7,853,235 entitled FIELD EFFECT TRANSISTOR WITH LINEARIZATION teaches a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance. Several inductors are required for realization of this circuit, and one of the inductors must be a tapped inductor. One disadvantage of requiring inductors is the size of the resulting circuit, which is particularly critical when the device is intended to be realized as an integrated circuit.
U.S. Pat. No. 6,717,463 entitled CIRCUITS FOR LINEARIZING ELECTRONIC CIRCUITS teaches a linearized amplifier circuit having a single bipolar transistor and a first series LC network connected between the common terminal of the transistor and ground, and a second series LC network connected between the input terminal of the transistor and ground. The linearization circuit does not interfere with the transistor amplification of an input RF signal. In the presence of two input signals or an input modulated carrier, the linearization circuit forces the control voltage between the input terminal and the common terminal of the transistor to be zero at the difference frequency of the two input signals or at a modulation frequency of the input modulated carrier. However, the use of the tuned LC network terminates the difference frequency at a specific frequency and thus it is not a wideband linearization solution. In addition, this method is only applicable to bipolar transistors where the difference frequency is present at the base of the transistor. For FETs, this linearization technique is not possible. The use of the LC network connected between the emitter of the main transistor and emitter of the current mirror instead of grounding these terminals may introduce unwanted feedback and thus this linearization method must be designed very carefully to avoid unwanted oscillation.
U.S. Pat. No. 6,531,924 entitled BIAS METHOD AND CIRCUIT FOR DISTORTION REDUCTION teaches a biasing circuit generating a direct current (DC) signal proportional to a selected nonlinearity, using the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero. This is implemented using multiple bias transistors each generating a DC current that is a portion of a DC signal proportional to a selected nonlinearity, a combining circuit that combines the DC currents to form the DC signal, and a feedback circuit to sense the DC signal and generate an input bias voltage of the bias transistors that serves to cancel the selected nonlinearity. However, the method proposed requires multiple FETs and a feedback sense circuit, thus increasing the overall periphery and die size. Additionally, the use of resistors as the feedback bias sense circuit at the source of the transistor degrades the gain and noise figure of the architecture.
U.S. Pat. No. 6,407,640 entitled TWO-STAGE LNA WITH GOOD LINEARITY teaches a two-stage bipolar low noise transistor amplifier architecture with a method for tailoring the inter-stage matching network to provide an optimum third order intercept point (OIP3). A process of simulation and analysis is used to determine the necessary values for the impedance transforming function of the inter-stage matching network. Disadvantages of this circuit include a high component count for the sensing, biasing and buffering circuitry, plus the complex process of simulation and analysis to determine the necessary component values.
U.S. Pat. No. 6,166,599 entitled IMPEDANCE MATCHING NETWORKS FOR NONLINEAR CIRCUITS teaches an active circuit wherein an impedance matching network is configured to cause the third-order intermodulation (IM3) products resulting from the even-order nonlinearity to approximately cancel the IM3 products resulting from the odd-order nonlinearity, and thereby provide a more linear output. However, this architecture requires careful selection of impedance matching networks for simultaneous linearization improvement and good output return loss. Typically, achieving both of these parameters simultaneously is difficult and a trade-off must be made. Additionally, the use of a matching network makes this a narrowband solution.
The technique of current mirror feedback has been successfully demonstrated in Heterojunction Bipolar Transistor (HBT) devices for improved dynamic range. The successful use of current mirror feedback in HBTs is due to the low frequency envelope appearing at the base of the HBT device. It is known that FETs cannot be linearized using this current mirror feedback method as the low frequency envelope appears at the drain of the FET. It would be desirable to have a method of current mirror feedback that improved linearization for FET amplifier circuits at radio frequencies without increasing the noise factor. FET amplifier circuits have several specific advantages over bipolar transistor amplifier circuits. First, biasing of a bipolar transistor must take into account thermal runaway conditions. A typical solution requires the addition of resistors to the base and emitter of the bipolar transistor which degrades the noise figure, gain and output power of the transistor. In contrast, FETs do not require this design consideration.
Second, the mechanism of bipolar transistors requires both electrons and holes as transport carriers, resulting in higher noise figures as compared to FETs, which require only electrons as the transport carrier.
Third, when used with a current mirror, bipolar transistors suffer from the Early effect because of the low current gain of the bipolar transistor. This results in complicated current mirror architectures to boost the current gain. In contrast, FETs have infinite current gain and do not suffer from the Early effect.
Fourth, FETs can be used at low supply voltages and linearity is still maintained at levels down to 1 volt. In contrast, the linearity of a bipolar transistor drops precipitously with decreasing supply voltage.
A higher-performing low-noise FET amplifier with high linearity would provide improved system dynamic range without the expense of increased power consumption, and the associated negative effects of increased power such as cost, size, and thermal management problems. Ideally, a FET amplifier linearization circuit would be realizable in a semiconductor topology with no degradation to other RF parameters including gain, IP3, P1dB, noise figure and return loss.